1. Field of the Invention
The present invention relates to a bias current compensation circuit and, more particularly, to a bias current compensation circuit applied for a differential input stage.
2. Description of the Related Art
Differential input stages are a well-known elementary electronic building functional block, widely applied in operational amplifiers, analog comparators, and the like. FIG. 1 is a detailed circuit diagram showing a conventional differential input stage 10. The differential input stage 10 is primarily formed by a pair of bipolar junction transistors (BJT) Q1 and Q2. The first transistor Q1 has a base electrode for serving as a first input terminal INa of the differential input stage 10 while the second transistor Q2 has a base electrode for serving as a second input terminal INb of the differential input stage 10. An emitter electrode of the first transistor Q1 and an emitter of the second transistor Q2 are coupled together and further coupled to a lower voltage rail V− through a current source IE1. A collector electrode of the first transistor Q1 is coupled to a higher voltage rail V+ through a resistor R1 while a collector electrode of the second transistor Q2 is coupled to the higher voltage rail V+ through a resistor R2. Moreover, a first output terminal OUTa of the differential input stage 10 is implemented by the collector electrode of the first transistor Q1 while a second output terminal OUTb of the differential input stage 10 is implemented by the collector electrode of the second transistor Q2.
As shown in FIG. 1, in a typical application of the operational amplifier or analog comparator, the first and the second input terminals INa and INb of the differential input stage 10 receive two independent voltage signals from a signal drive circuit 11, respectively. One of the two voltage signals may be a variable drive signal and the other may be a constant reference signal, or both of them are variable drive signals. In response to a difference between the first and the second voltage signals at the first and the second input terminals INa and INb, the first and second output terminals OUTa and OUTb generates an amplified signal or a compared result to be supplied to an output application circuit 12.
During the amplifying or comparing operation performed by the differential input stage 10, the first and the second transistors Q1 and Q2 need to be turned on or off in accordance with the first and the second voltage signals received at the first and the second input terminals INa and INb. For example, when the first voltage signal received at the first input terminal INa is higher than the second voltage signal received at the second input terminal INb, the first transistor Q1 needs to be turned on by a first bias current IBa such that the current source IE1 flows through the conductive first transistor Q1. When the second voltage signal received at the second input terminal INb is higher than the first voltage signal received at the first input terminal INa, the second transistor Q2 needs to be turned on by a second bias current IBb such that the current source IE1 flows through the conductive second transistor Q2.
As to the conventional application shown in FIG. 1, the first and the second bias currents IBa and IBb must be provided by the signal drive circuit 11. Since the demand of the first bias current IBa and the demand of the second bias current IBb do not occur simultaneously, the signal drive circuit 11 induces a voltage error between the first and the second input terminals INa and INb. Furthermore, due to the trend of developing a higher responsive speed of the differential input stage 10, the signal drive circuit 11 is required to provide a much higher bias current IBa or IBb. However, a larger error and a nonlinear effect are inevitably caused by the signal drive circuit 11 due to the burden of providing the much higher bias current IBa or IBb, resulting in that the differential input stage 10 fails to achieve accurate operations.